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CA-Santa Clara, Description: Looking for Senior ASIC Verification Engineer who has extensively worked on complex SoCs using SystemVerilog/OVM , verilog, C and perl. You must be proficient in writing test cases, debugging RTL using System verilog based random and direct testing The following are the requirements: Experience in writing testbenches, creating verification environment using Systemverilog Good experien
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| Senior ASIC Verification Engineer - OVM/RVM | ||||